The present invention relates to a semiconductor device testing apparatus and test method for cases where an AC test, etc., is conducted on a semiconductor device using a binary search method.
A semiconductor testing apparatus has long been known as an apparatus for conducting tests on various kinds of semiconductor devices such as pre-shipment logic ICs and semiconductor memories. Tests conducted by this semiconductor testing apparatus include a function test, AC parametric test, and DC parametric test. Of these, the AC parametric test evaluates AC parameters such as time-axis characteristics and frequency characteristics of a semiconductor device which is the DUT (Device Under Test), and a method called a binary search is known as a typical test method.
FIG. 5 is a flowchart showing the conventional processing procedure for finding the pass/fail threshold value of a semiconductor device using the binary search method. As an example, the case will be considered where, for a normal semiconductor device, a pass is obtained as the measurement result when the measurement point is set to the upper-limit value of the test range, and a fail is obtained as the measurement result when the measurement point is set to the lower-limit value of the test range, and the pass/fail threshold value is searched for between these upper-limit and lower-limit values.
(1) First, the pass value PV is set to the upper-limit value of the test range (step 200), the output value of the Device Under Test at the measurement position corresponding to this pass value is examined (step 201), and a pass is confirmed (step 202). If the Device Under Test does not pass, the prescribed error processing is performed (step 203).
(2) Similarly, the fail value FV is set to the lower-limit value of the test range (step 204), the output value of the Device Under Test at the measurement position corresponding to this fail value is examined (step 205), and a fail is confirmed (step 206). If the Device Under Test does not fail, the prescribed error processing is performed (step 207).
(3) The next measurement point is set to (PV+FV)/2, (step 208), the output value of the Device Under Test at this measurement position is examined (step 209), and a check is made of whether the Device Under Test has passed or failed (step 210). If the measurement result is a pass, the current measurement position (PV+FV)/2 is assigned to the pass value PV (step 211). If, on the other hand, the measurement result is a fail, the current measurement position (PV+FV)/2 is assigned to the fail value FV (step 212).
(4) The processing described in (3) above is repeated until the absolute value of the difference between the pass value PV and the fail value FV, |PV−FV|, is equal to or less than the resolution RE (step 213).
Now, according to the conventional method using the binary search method, measurements at the upper-limit value and lower-limit value of the test range are performed in order to confirm that the Device Under Test is normal, and there is little possibility of the pass/fail threshold value lying outside this test range. With the actual values obtained in actual testing, the proportion of cases in which a fail is at the upper limit of the test range, or a pass is at the lower limit of the test range, is several percent. Therefore, with the conventional method using the binary search method, there is a problem of a long testing time due to the execution of inefficient confirmation work in which results that are a matter of course are obtained. When a large number of Devices Under Test are tested consecutively, in particular, the individual test times accumulate, and a method is therefore desirable that will allow at least somewhat more efficient testing to be carried out, and the overall test time to be shortened.